1. Field of the Invention
The present invention relates to testing of semiconductor devices, and more particularly to process monitor structures for accurately predicting the performance of an integrated circuit with respect to simulations.
2. Description of the Related Art
Integrated circuits have become key components of many consumer and commercial electronic products, often replacing discrete components and enhancing product functionality. The semiconductor processing technologies that produce these integrated circuits have advanced to the point where complete systems can now be reduced to a single integrated circuit or application specific integrated circuit (ASIC) device. These integrated circuits (also referred to as "chips") may use many functions that previously could not be implemented together on a single chip, including: microprocessors, digital signal processors, mixed signal and analog functions, large blocks of memory and high speed interfaces. It is a common practice for the manufacturers of such integrated circuits to thoroughly test device functionality at the manufacturing site. However, the complex nature of today's integrated circuits presents new testing challenges.
Interconnecting the millions of logic gates and megabytes of memory that may be present on a chip also poses difficulties. To aid in this task, new multiple layer metallization schemes have been developed that allow up to five or more distinct "levels" or layers of metal interconnect wires, with pitches of 0.125 .mu.m and tighter on the first few layers. In such multiple layer metallization schemes, the various metal interconnect wires typically have different nominal widths and heights, different distances from transistor gates, and are insulated by oxide layers of varying thickness. These differences in the physical properties of the metal layers cause different metal layers to exhibit somewhat dissimilar electrical characteristics, resulting in disparities in propagation delays that a signal experiences when communicated over routing wires formed from the different metal layers.
Often, the performance of the integrated circuitry can be dominated by propagation delays through longer metal interconnect wires rather than the basic gate delays of individual logic elements. This phenomenon is exacerbated by the fact that as the width of a wire shrinks in deep submicron designs, the resistance of the wire increases more rapidly than capacitance decreases. It has been estimated that interconnect delays may thus determine as much as 70-80% of the total delay in integrated circuits implemented in 0.25 .mu.m process rules. An increase in average propagation delays frequently results in a greater number of critical timing paths (e.g., signal paths in which best or worst case simulated propagation delays may approach the limits required for proper functionality). Many timing problems involve such critical timing paths.
In order to avoid timing and other problems, integrated circuits are typically simulated in a software environment, using a variety of CAE tools, before the integrated circuits are actually fabricated. Such simulations function to reduce costly design iterations because modifications to an integrated circuit design are more readily achieved in software. Given the complexity of today's integrated circuits, accurate simulation is thus essential to a successful integrated circuit design.
Following fabrication of an integrated circuit, testing is performed to insure that the integrated circuit functions as designed. Although the integrated circuit may work functionally, it may not operate at the proper frequency at which it was designed to operate. Certain testing methodologies are employed to verify that the integrated circuit works "at speed." One such method is to test all circuitry functionally at the highest frequency at which the integrated circuit is designed to operate. At speed testing is typically not performed, however, because it is extremely difficult to create test patterns to check integrated circuits at high frequencies. Further, specialized testers are also required. Under test conditions, the shortest directly measurable path in a high performance integrated circuit design is typically less than 10 ns. Measurement inaccuracies in automatic testing equipment and analog effects in the testing environment can represent a large portion of such time (the observable path), thus rendering the test meaningless.
As a result, another method used to verify at speed functionality involves measuring predetermined critical paths and assume that if these critical paths meet the timing specifications, all other paths are within specification. However, identification and measurement of critical paths is sometimes difficult.
To address these difficulties, process monitoring circuitry has been developed that resides on the integrated circuit itself. One such process monitor is the "PROCMON" cell developed by LSI Logic Corporation of Milpitas, Calif. The PROCMON circuits are tested and their performance serves as a parametric test of the integrity of the manufacturing process.
In complementary metal-oxide-semiconductor (CMOS) circuits, the performance of the integrated circuit depends on the performance of both p-channel (PMOS) and n-channel (NMOS) transistors. Since the PMOS and NMOS transistors are formed at different stages of the manufacturing process, process variations at a given step may not affect the PMOS and NMOS transistors equally. As explained more fully below in the detailed description of the present invention, the PROCMON cell includes a short and long delay paths providing a first edge delay pulse in response to a logic level high to a logic low transition signal at the input terminal, and providing a second edge delay pulse when a logic low to logic high transition signal is provided at the same input terminal. The differences between the edge delay pulses are indicative of the relative performance of the PMOS and NMOS transistors being monitored.
However, given the increased length of routing that is frequently encountered in today's integrated circuits, the PROCMON cell may not take into account delays associated with long metal lines and/or a multitude of vias in certain delay paths. The PROCMON cell does monitor "short" and "long" signal paths, however the "long" signal path is typically contained within the cell itself and may not reflect actual routing. Because the long metal paths are contained within the PROCMON cell, length of routing and the number of vias that can be utilized are also limited. Further, process monitor circuits such as the PROCMON cell are typically routed in the first layer of interconnect metal, such that resistance changes between the vias connecting this layer of metal and second layer and third layer (or more) metals, or resistance changes in the other metal layers themselves do not get monitored. Thus, the load on the output of one transistor may be accounted for in simulation, but the length of the metal line or number of vias needed would not be accurately simulated. Therefore, if a process problem develops that effects the resistance or capacitances of different metal layers or vias, the current process monitors may not detect such problems. More specifically, no attempt is currently made to measure either the resistances or capacitances of long metal lines (with many vias) on different metal layers.